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許明華老師的論文著述 一、學術期刊論文 - 許明華, 2023, Wide operation range high-voltage linear regulator chip design, Electrical Engineering. (SCI)
- 許明華, 2023, Portable RDFT-Based EIS System Design with a Low-Complexity Impedance Calculation, IEEE Trans. on Instrumentation & Measurement, Vol.72, pp.1-15. (SCI)
- 許明華, 2023, Improvement of Human Pose Estimation and Processing With the Intensive Feature Consistency Network, IEEE Access, Vol.11, pp.28045-28059. (SCI)
- 許明華, 2022, Lightweight Denoising Autoencoder Design for Noise Removal in Electrocardiography, IEEE Access, Vol.10, p98104~98116. (SCI)(用於互動式健身肌力效能評比之智慧物聯網系統開發, 110-2622-E-224-006-, 110-3011-1)
- 許明華, 2022, FIBS-Unet: Feature Integration and Block Smoothing Network for Single Image Dehazing,, IEEE Access, Vol.10, pp.71764~71776. (SCI)(基於2D視訊與穿戴感測器融合之多人體動作識別與比對系統晶片設計, 110-2221-E-224 -052 -MY2, 110-1125-2)
- 許明華, 2022, Channel-Wise Average Pooling and 1D Pixel-Shuffle Denoising Autoencoder for Electrode Motion Artifact Removal in ECG, Applied Sciences, Vol.12, pp.1~22. (SCI)(用於互動式健身肌力效能評比之智慧物聯網系統開發, 110-2622-E-224-006-, 110-3011-1)
- 許明華, 2022, Hardware Accelerator Design of DCT Algorithm With Unique-Group Cosine Coefficients for Mel-Scale Frequency Cepstral Coefficients,, IEEE Access, Vol.10, pp.71764~71776. (SCI)
- 許明華, 2022, Integration Design of Portable ECG Signal Acquisition with Deep-Learning Based Electrode Motion Artifact Removal on an Embedded System,, IEEE Access, Vol.10, pp.57555~57564. (SCI)(用於互動式健身肌力效能評比之智慧物聯網系統開發, 110-2622-E-224-006-, 110-3011)
- 許明華, 2022, Area-efficient multi-channel active matrix micro-LED driver chip design, Analog Integrated Circuits and Signal Processing. (SCI)
- 許明華, 2022, A Low-cost Smart Digital Mixer System Based on Speech Recognition, Electronics, pp.1~11. (SCI)(基於2D視訊與穿戴感測器融合之多人體動作識別與比對系統晶片設計, 110-2221-E-224 -052 -MY2, 110-2622-E-224 -006, 110-1125-1)
- 許明華, 2022, FHI-Unet: Faster Heterogeneous Images Semantic Segmentation Design and Edge AI Implementation for Visible and Thermal Images Processing, IEEE Access, Vol.10, pp.18596 - 18607. (SCI)(基於2D視訊與穿戴感測器融合之多人體動作識別與比對系統晶片設計, 110-2221-E-224 -052 -MY2, 110-2622-E-224 -006, 110-1125-1)
- 許明華, 2021, FGSC: Fuzzy Guided Scale Choice SSD Model for Edge AI Design on Real-Time Vehicle Detection and Class Counting, Sensors, pp.1~21. (SCI)(基於2D視訊與穿戴感測器融合之多人體動作識別與比對系統晶片設計, 110-2221-E-224 -052 -MY2, 110-2622-E-224 -006, 110-1125-1)
- 許明華, 2021, A 0.3V PNN based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications, Sensors, pp.1~21. (SCI)(基於2D視訊與穿戴感測器融合之多人體動作識別與比對系統晶片設計, 110-2221-E-224 -052 -MY2, 110-2622-E-224 -006, 110-1125-1)
- 許明華, 2021, UAV Object Tracking Application Based on Patch Color Group Feature on Embedded System, Electronics, pp.1~10. (SCI)(基於2D視訊與穿戴感測器融合之多人體動作識別與比對系統晶片設計, 110-2221-E-224 -052 -MY2, 110-2622-E-224 -006, 110-1125-1)
- 許明華, 2021, Fast-Transient High-Voltage Buck-Boost DC-DC Conversion with Low Overshoot, Microelectronics Journal. (SCI)
- 許明華, 2021, Stable Local Bit-Line 6 T SRAM Architecture Design for Low-Voltage Operation and Access Enhancement, Electronics, pp.1~11. (SCI)(用於可見光和熱感雙攝影機的深度學習物件偵測和融合之SoC設計, 109-2221-E-224 -050, 109-1094)
- 許明華, 2021, A Novel Cross-Latch Shift Register Scheme for Low Power Applications, Applied Sciences.
- 許明華, 2020, A new low-complexity approximate DCT for image and video compression, Journal of the Chinese Institute of Engineers, pp.580-591.
- 許明華, 2020, Cost-Effective LED Dimming Driver With Single Chip Design for Smart Lighting System, IEEE Access, pp.141025-141032.
- 許明華, 2020, A Prototype Design of ECG and EMG Acquisition System with Novel Lossless Data Compression and Baseline Wandering Cancellation Algorithms, International Journal of. Electrical Engineering ISSN, pp.77-97.
- 許明華, 2019, Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design, IEICE Transactions on Electronics, No.11, pp.833-838.
- 許明華, 2019, Low Complexity and Low Power Sense- Amplifier Based Flip-Flop Design, IEICE Transactions on Electronics, No.11, pp.833-838.
- 許明華, 2019, A Fast Non-overlapping Multi-camera People Re-identification Algorithm and Tracking Based on Visual Channel Model, IEICE TRANSACTIONS on Information and Systems, Vol.E102-D, No.7, pp.1342-1348.
- 許明華, 2018, An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme, 2018 IEEE International Symposium on Circuits and Systems, pp.1-4.
- 許明華, 2017, Low Power 19-Transistor True Single Phase Flip-Flop Design Based on Logic Structure Reduction Schemes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.25, No.11, pp.3033 - 3044. (SCI)
- 許明華, 2017, Fast Motion Object Detection Algorithm Using Complementary Depth Image on an RGB-D Camera, IEEE Sensors Journal, Vol.17, No.17, pp.5728 - 5734. (SCI)
- 許明華, 2017, Efficient Reverse Converter Design for the New Four-moduli Set {22n, 2n+1, 2n/2+1, 2n/2−1}, Journal of the Chinese Institute of Engineers, Vol.40, No.2, pp.1-7. (SCI)
- 許明華, 2016, New Adaptable Three-Moduli Set {2n+k, 2n − 1, 2n−1 − 1} for Residue Number System-Based Finite Impulse Response Implementation, IEICE Electronics Express, Vol.13, No.11, pp.1-9. (SCI)
- 許明華, 2016, New Reverse Converter Design for 4-Moduli Set{ 2 2n, 2 n+1 − 1, 2 n/2 + 1, 2 n/2 − 1 }, ICIC Express Letters, Part B, Vol.7, No.5, pp.1111-1117. (EI)
- 許明華, 2015, A Novel Flexible 3D Heterogeneous Integration Scheme Using Electro-less Plating on Chips with Advanced Technology Node, IEEE Transactions on Electron Devices, Vol.62, No.12, pp.4148-4153.
- 許明華, 2015, Chip Implementation of High-Efficient LED Dimming Driver for High-Power LED Lighting, IET Power Electronics, Vol.6, No.6, pp.1043-1051.
- 許明華, 2015, New Efficient Reverse Converter for 3-Moduli Set {22n, 2n+1, 2n-1} Based on New CRT-I, ICIC Express Letters. (EI)
- 許明華, 2015, A Single ended Structure Sense Amplifier based Flip-Flop Design for Low Power Systems, IET Electronics Letters, Vol.51, No.1, pp.20-21.
- 許明華, 2014, Fast Image Foreground Object Segmentation based on BlockTexture for Embedded System Implementation, Journal of the Chinese Institute of Engineers. (SCI)
- 許明華, 2014, Embedded Temperature Sensor for Multilevel Current LED Driver, IEEE Sensors Journal, Vol.14, No.8, pp.2801-2806. (SCI)
- 許明華, 2014, Efficient Block-based Dynamic Background Modeling and Foreground Object Detection in the DCT Domain, ICIC Express Letters, Part B, Vol.5, No.2, pp.203-208. (EI)
- 許明華, 2013, Reverse to Binary Converter for 4-moduli set {22n, 22n+1-1, 2n+1, 2n-1} Based on CRT-II, ICIC Express Letters, Vol.4, No.5, pp.1-6. (EI)
- 許明華, 2013, Fast Image Foreground Object Segmentation based on Block Texturefor Embedded System Implementation, Journal of the Chinese Institute of Engineers. (SCI)
- 許明華, 2013, ”New Flexible Four-Moduli Set {2n+k,2n +1,2n +1,22n +1}and Efficient Reverse Converter Design, IEICE Tran. on Fundamentals of Electronics, Communications and Computer Sciences,, Vol.E96-A, No.7. (SCI)
- 許明華, 2013, Efficiency Reverse Converter for 4-Moduli Set {22n, 22n+1-1, 2n+1, 2n-1} Based on New CRT-II, Applied Mechanics and Materials, Vol.336-368, pp.1852-1856. (EI)
- 許明華, 2013, An Arrow Poniter Sensor Design for Low-Cost Water-Meter, IEEE Sensors Journal, Vol.13, pp.1852-1856. (SCI)
- 許明華, 2013, High-Performance Local Dimming Algorithm and Its Hardware Implementation for LCD Backligh, IEEE Journal of Display Technology, pp.1-9. (SCI)(多色溫調變LED之智慧節能路燈系統研發-總計畫暨子計畫三:智慧型LED路燈控制與道路監視之SoC系統設計研究)
- 許明華, 2012, Block-Based Major Color Method for Foreground Object Detection on Embedded SoC Platforms, IEEE Embedded Systems Letters, Vol.4, No.2, pp.49-52. (SCI)(多色溫調變LED之智慧節能路燈系統研發-總計畫暨子計畫三:智慧型LED路燈控制)
- 許明華, 2012, High-Accuracy Background Model for Real-Time Video Foreground Object Detection, Optical Engineering. (SCI)(多攝影機人車監控之SoC嵌入式系統(II))
- 許明華, 2012, Low Power Pulse-Triggered Flip-Flop Design with Conditional Pulse Enhancement Scheme, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol.20, No.20. (SCI)(多攝影機人車監控之SoC嵌入式系統(II))
- Chung-Chi Lin, Ming-hwa Sheu, Huann-keng Chiang, and Chishyan Liaw, 2010, Fast First-order Polynomials Convolution Interpolation for Real-time Digital Image Reconstruction, IEEE Transactions on circuits and systems for video technology, Vol.20, No.9, 1260-1264. (SCI)
- Jin-Fa Lin, Yin-Tsung Hwang and Ming-Hwa Sheu, 2010, Low Power Pulse Generator Design Using Hybrid Logic, IEICE Transaction on Fundamentals, Vol.E-93-A, No.6, pp.1266-1268. (SCI)
- Jin-Fa Lin, Yin-Tsung Hwang and Ming-Hwa Sheu, 2010, A low complexity low power signal transition detector design for self-timed circuits, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E-93-A, No.4, pp.843-845. (SCI, EI)
- C.C. Lin, M.H. Sheu, H.K. Chiang, C. Liaw, Z.C.huan Wu, and W.K. Tsai, 2010, An Efficient Architecture of Extended Linear Interpolation for Image Processing, Journal of Information Science and Engineering, Vol.1, No.1, pp.631-648. (SCI)
- Chung-chi Lin, Ming-hwa Sheu, Huann-keng Chiang, Chishyan Liaw, and Zeng-chuan Wu, 2008, An efficient convolution interpolation kernel for digital image scaling, IEICE Electronics Express, Vol.5, No.20, pp.860-864. (SCI)
- S.H. Lin, M.H. Sheu, 2008, VLSI Design of Diminished-One Modulo 2^n+1 Adder Using Circular Carry Selection, IEEE Trans. On Circuits & SystemsⅡ, Vol.55, pp.897-901. (SCI)
- J.F. Lin, Y.T. Hwang, M.H. Sheu, 2008, Low Complexity Dual-Mode Pulse Generator Designs, IEICE Trans. On Fundamentals of Electronics, Communications and Computer Sciences, Vol.E91-A, pp.1812-1815. (SCI)
- S.H. Lin, M.H. Sheu, 2008, Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set(2^n, 2^n+1-1, 2^n-1), IEICE Trans. On Fundamentals of Electronics, Communications and Computer Sciences, Vol.E91-D, pp.2058-2060. (SCI)
- S.H. Lin, M.H. Sheu, 2008, Area-Time Efficient Modulo 2n-1 Adder Design Using Hybrid Carry Selection, IEICE Trans. On Information & Systems, Vol.E91-D, pp.361-362. (SCI)
- C.C. Lin, M.H. Sheu, H.K. Chiang, C.J. Wei and C. Liaw, 2007, A High-performance Architecture of Motion Adaptive De-interlacing, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E90-A, No.11, pp.2575-2583. (SCI)
- J. F. Lin, Y. T. Hwang, M. H. Sheu, C. C. Ho, 2007, A Novel High Speed and Energy Efficient 10-Transistor Full Adder Design, IEEE Trans. on Circuits & Systems I, Vol.54, No.5, pp.1050-1059. (SCI)
- C. C. Lin, M. H. Sheu, H. K. Chiang, and C. Liaw, 2005, Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection, PCM 2005,Lecture Notes in Computer Science, Vol. 3767, pp. 291-302. (SCI)
- M.H.Sheu, S.H.Lin, C.Chen and S.W.Yang, 2004, An Efficient VLSI Design for a Residue to Binary Converter for General Balance Moduli(2^n-3,2^n+1,2^n-1,2^n+3), IEEE Trans. on Circuits and Systems II:Analog and Digital Signal Processing, Vol. 51, No. 3, pp. 152-155. (SCI)
- 黃新武, 許明華, 王文魁, 洪俊傑, 2004, 光學滑鼠控制晶片設計與量測, e-科技雜誌, Vol. 45, No. 1, pp.25-27.
- Chichyang Chen, H. L. Yen, and M. H. Sheu, 2004, Design of a Cost-Effective Multiplier / Divider Fused Unit for Floating-Point Arithmetic, International Journal of Electrical Engineering, Vol.11, No.3, pp.239-246. (SCI)
- Chichyang Chen, H.L.Yen, and M.H.Sheu, 2004, Design of a New Multiplier/Drivider Fused Unit for Floating-Point Arithmetic, Revised in International Journal of Electronical Engineering, Vol. 11, No. 3, pp.25-27. (EI)
- M.H.Sheu and Y.T.Shih, 2004, A Low Cost Direct Digital Frequency Synthesizer Based on Rescursive Trigonometric Approach, Journal of Science and Technology, Vol. 13, No. 3, pp. 197-202.
- Chichyang Chen, R.L.CHen and M.H.Sheu, 2004, A Fast Additive Normalization Method for Exponential Computation, IEE Processings on Computer and Digital Techniques, Vol. 151, No. 3, pp.191-198. (SCI)
- M.H.Sheu, H.E.Liao, and S.T.Kan, 2003, VLSI Design of Fast Adaptive Frequency Detection for the Noisy Sinusoid, Revised by Europe Applied Signal Processing. (SCI)
- M.H.Sheu, H.E.Liao and S.T.Ksn, 2003, VLSI Architecture Design for On-Line Frequency Detection of Single Sinusoid, Journal of the Chinese Institute of Electrical Engineering, Vol. 10, No. 2, pp. 175-181. (EI)
- M.H.Sheu, and S.H.Lin,, 2002, An Efficient VLSI Design of MRC-Based Residue to Binary Converters for Specific Moduli sets, Journal of Science and Technology, Vol. 11, No. 3, pp. 181-186.
- M.H.Sheu, and S.H.Lin, 2002, Fast Compensative Design Approach for the Approximate Squaring Function, IEEE Journal of Solid-State Circuits, Vol. 37, pp. 95-97. (SCI)
- M. D. Shieh, M. H. Sheu, C. H. Chen and H. F. Lo, 2001, A Systematic Approach for Parallel CRC Computations, Journal of Information Science and Engineering, Vol.1, pp. 445-461. (SCI, EI)
- M.H. Sheu, J.S. Lin, S.S. Yang, J.Y. Lin, and M.H. Lin, 2001, A Modified Compeitive Learning Network in Image Compression and VLSI Implementation, Journal of Science and Technology, Vol. 10, No. 1, pp. 23-28.
- M. H. Sheu, and S. H. Lin, 2000, A High Performance VLSI Design of Fast Convolution Computation, Journal of Science and Technology, Vol. 9, No. 4, pp. 263-268.
- M.H. Sheu, J.F. Wang, and J.Y. Lee, 1993, The Determination of the Cycle Length in High Level Synthesis, International Journal of VLSI Integration, Vol. 16, No. 2, pp. 131-148. (SCI, EI)
- M.H. Sheu, J.F. Wang, J.C. Chen, A.N. Suen, Y.L. Jeang, and J.Y. Lee, 1992, A Data-Reuse Architecture for Gray-Scale Morphologic Operations, IEEE Transactions on Circuits and Systems, Vol. 39, No. 10, pp. 533-536. (SCI)
- J.F. Wang, M.H. Sheu, Y.L. Jeang, W.Y. Lee and J.Y Lee, 1992, Automatic Design of Microprogrammed Controllers for Multicycling and Chaining Operation, Proceedings of the National Science Council, Vol. 16, No. 4, pp. 331-339.
二、研討會論文- 許明華, 2023, VLSI Design for Low-power and Wide-band Programmable Frequency Divider, 2023 IEEE 5th Eurasia Conference on IOT, Communication and Engineering (ECICE), 2023/10/27-29, IEEE, Yunlin.
- 許明華, 2023, Fast Measurement of Impedance Calculation for Electrochemical Impedance Spectroscopy, 2023 20th International SoC Design Conference (ISOCC), 2023/10/25-28, IEEE, Jeju.
- 許明華, 2023, Heart Valve Disease Recognition Using Phonocardiogram Signal Based on A Lightweight Convolution Neural Network, 2023 20th International SoC Design Conference (ISOCC), 2023/10/25-28, IEEE, Jeju.
- 許明華, 2023, Convolutional Neural Network-based Keyword Classification for Mixer Control, 2023 20th International SoC Design Conference (ISOCC), 2023/10/25-28, IEEE, Jeju.
- 許明華, 2023, Unique Feature Extraction and Consistency Network for Skeleton Body Keypoints Configuration and Enhancement, 2023 IEEE 6th International Conference on Knowledge Innovation and Invention (ICKII), 2023/08/11-13, IEEE, Sapporo.
- 許明華, 2023, A Low-Complexity Convolution Network for Upscale Super-Resolution Image, 2023 IEEE 6th International Conference on Knowledge Innovation and Invention (ICKII), 2023/08/11-13, IEEE, Sapporo.
- 許明華, 2021, Improved Transform Algorithm of Direct Computation of Discrete Cosine for Mel-scale Frequency Cepstral Coefficient, 2021 International Conference on Electronic Communications, Internet of Things and Big Data (ICEIB), 2021/12/10-12, IEEE, 宜蘭.
- 許明華, 2021, A Novel Low-cost Smart Digital Mixer System Based on Speech Recognition, The 3rd International Symposium on Engineering and Technology (ISET 2021), 2021/11/19-20, 國立中興大學, 台中市, 國立中興大學.
- 許明華, 2021, A Novel Bird Detection and Identification based on DPU processor on PYNQ FPGA, 2021 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), 2021/09/15-17, IEEE, 澎湖.
- 許明華, 2021, AIoT-based Audio Recognition System for Smart Home Applications, 2021 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), 2021/09/15-17, IEEE, 澎湖.
- 許明華, 2021, Font-End Integrated Circuit Design for Plant Physiological Sensing, 2021 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), 2021/09/15-17, IEEE, 澎湖.
- 許明華, 2021, Software and Hardware Integration System Design with Fruit Identification for Smart Electronic Scale Applications, 2021 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), 2021/09/15-17, IEEE, 澎湖.
- 許明華, 2021, Real-time Stereo Television Broadcasting System, 2021 IEEE International Conference on Consumer Electronics (ICCE), 2021/01/10-12, IEEE, Las Vegas, NV.
- 許明華, 2019, An Efficient VLSI Architecture Design for Real-time Image Object Tracking Applied to UAV, 2019 VLSI Design/CAD Symposium, 2019/08/06-09, 臺灣積體電路設計學會, 高雄義大皇家酒店.
- 許明華, 2019, Capacitance-Mismatch-Calibration-Algorithm-based-on-Least-Square-and-Iterative-Methods-for-an-Energy-efficient-Monotonic-Switching-SAR-ADC, 2019 VLSI Design/CAD Symposium, 2019/08/06-09, 臺灣積體電路設計學會, 高雄義大皇家酒店.
- 許明華, 2019, The Image Shape Recovery on Communication Data Lost Damage, Intl. Conf. on Ubiquitous and Future Networks, 2019/07/02-05, IEEE, Split, Croatia.
- 許明華, 2019, Low -Power Counter-Based Delay Line Design For DPWM, IEEE Intl. Conf. on Consumer Electronics - Taiwan, 2019/05/20-22, ICCE-TW, 宜蘭常綠度假村酒店.
- 許明華, 2019, Implementation of FPGA-based Accelerator for Deep Neural Networks, IEEE Design and Diagnostics of Electronic Circuits and Systems, 2019/04/24-26, IEEE, Cluj · Romania.
- 許明華, 2018, Lighter sound recognition, 2018 Conference on Applications of Innovation and Invention (AII2018), 2018/11/23, AII2018, 臺中市,國立勤益科技大學, pp.22-25.
- 許明華, 2018, A High-Efficient Architecture Design of Shift Register Using Cross-Coupling Scheme, 2018 Taiwan and Japan Conference on Circuits and Systems, 2018/08/02, TJCAS 2018, Taichung.
- 許明華, 2018, Moving Object Tracking Algorithm Design for Unmanned Aerial Vehicle Platform, 2018 IEEE International Conference on Consumer Electronics-Taiwan, 2018/05/19-21, ICCE-TW, Taichung, pp.1-2.
- 許明華, 2018, Intelligent Design for Sound Detection of Goblet Clinking, 2018 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), 2018/05/19-21, IEEE, Taichung, pp.1-2.
- 許明華, 2018, Bike Sensor System Design for Safety and Healthy Riding, 2018 IEEE International Conference on Consumer Electronics-Taiwan, 2018/05/19-21, IEEE, Taichung, pp.1-2.
- 許明華, 2017, Real-time moving object tracking for UAV platform, The 30th IPPR Conf. on CVGIP, 2017/08/21-23, IPPR, 南投縣杉林溪, pp.A1-3.
- 許明華, 2017, High-performance Reverse Converter Design for the New Four-moduli Set {22n, 2n +1, 2n/2+1, 2n/2−1}, IEEE Conference on Dependable and Secure Computing, 2017/08/07-10, IEEE, Taipei, Taiwan, pp.541-542.
- 許明華, 2017, Object Tracking Algorithm and Embedded System Design From Non-Overlapping Multiple Cameras, The 28th VLSI Design/CAD Symp, 2017/08/01-04, 臺灣積體電路設計學會, 屏東,墾丁, pp.1-3.
- 許明華, 2017, Application of Thermal Camera in PV Plants Shelter Detection, 2017 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2017/06/12-14, IEEE, Taipei. Taiwan, pp.413-414.
- 許明華, 2017, Non-overlapping Multi-camera Object Tracking Algorithm and System Design, 2017 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2017/06/12-14, IEEE, Taipei. Taiwan, pp.411-412.
- 許明華, 2017, System on Programmable Chip Design for FMCW Radar Signal Processing, Progress in Electromagnetics Research Symposium, 2017/05/22-25, PIERS OFFICE, St Petersburg. Russia, pp.122-125.
- 許明華, 2017, 應用熱像儀之太陽能板遮陰物偵測, 第十六屆離島資訊技術與應用研討會, 2017/05/19-21, 國立金門大學資訊工程&電子工程學系, 金門.
- 許明華, 2016, 可調餘數模組{2n+k , 22n+1-1, 2n -1}之低功率餘數轉回二進制轉換器設計, International Conference on Safety & Security Management and Engineering Technology 2016, 2016/12/02, 吳鳳科技大學, 嘉義縣,吳鳳科技大學.
- 許明華, 2016, Edge-based moving Object Tracking Algorithm for an Embedded System, The IEEE APCCAS 2016, the 13th of the biennial Asia Pacific Conference on Circuits and Systems, 2016/10/25-28, IEEE, Jeju Island,RAMADA PLAZA JEJU Hotel.
- 許明華, 2016, High efficient hardware allocation framework of arbitrary inverse transform coding blocks in H.265, 2016 International Symposium on Intelligent Signal Processing and Communication Systems, 2016/10/24-27, Prince of Songkla University, Phuket Thailand.
- 許明華, 2016, VLSI Architecture Design and Implementation Based on Edge-based Moving Object Tracking Algorithm, The 27th VLSI Design/CAD Symp, 2016/08/02-05, 臺灣積體電路設計學會, 高雄市,君鴻國際酒店.
- 許明華, 2016, An Efficient Foreground Object Detection Method Using a Color Cluster-Based Background Modeling Algorithm, 2016 International Symposium on Computer, Consumer and Control (IS3C), 2016/07/04-06, National Chin-Yi University of Technology, 中國大陸,西安市.
- 許明華, 2016, Object detection using adaptive block-based background model, Consumer Electronics-Taiwan (ICCE-TW), 2016 IEEE International Conference on, 2016/05/27-29, 經濟部(國際貿易局), 南投縣,國立暨南大學.
- 許明華, 2016, Intelligent system design for variable color temperature LED street light, 2016 IEEE International Conference on Consumer Electronics-Taiwan, 2016/05/27-29, 經濟部(國際貿易局), 南投縣,國立暨南國際大學.
- 許明華, 2016, 新4餘數模組{22n , 22n-1-1 ,2n +1 ,2n -1}之高效能反轉換器設計, 第十五屆離島資訊技術與應用研討會, 2016/05/20-21, 樹德科技大學資訊工程系, 高雄市,樹德科技大學.
- 許明華, 2015, 具有低功率與高效能之感測放大正反器設計與晶片實現, 智慧電子應用設計研討會, 2015/11/30, 高應大, 高應大, p.39.
- 許明華, 2015, 改良式RNS-based FIR之設計, WCE2015 民生電子研討會, 2015/11/28, 建國科技大學, 彰化.
- 許明華, 2015, Moving Object Detection System Design base on Varible Block Background Modeling, Int. Conf. on Innovation ,Communication and Engineering, 2015/10/23-28, Fuzhou University, 中國長沙, pp.155-158.
- 許明華, 2015, New Reverse Converter Design for 4-Moduli set {22n, 2n+1-1, 2n/2+1, 2n/2-1}, Int. Conf. on Innovative Computing, Information and Control, 2015/08/20-22, ICIC International, 中國大連, pp.231-234.
- 許明華, 2015, 可調式區塊背景模型建立與前景物件偵測, 第十四屆離島資訊技術與應用研討會, 2015/05/22-23, 國立澎湖科技大學資訊工程系, 澎湖, pp.540-548.
- 許明華, 2015, 基於Kincet 人體骨架與OpenCV 人臉偵測技術實現幼童判別, 第十四屆離島資訊技術與應用研討會, 2015/05/22-23, 國立澎湖科技大學資訊工程系, 澎湖, pp.536-539.
- 許明華, 2015, 數位式控制之高壓降壓轉換器晶片設計, 第十四屆離島資訊技術與應用研討會, 2015/05/22-23, 國立澎湖科技大學資訊工程系, 澎湖, pp.532-535.
- 許明華, 2015, 具UART 調光介面之LED 多階電流驅動晶片設計, 第十四屆離島資訊技術與應用研討會, 2015/05/22-23, 國立澎湖科技大學資訊工程系, 澎湖, pp.528-531.
- 許明華, 2014, 結合Kinect資訊之影像移動物件偵測, 智慧電子應用設計研討會, 2014/12/04, 智慧電子應用設計(IED)聯盟, 高雄市,高應大.
- 許明華, 2014, 應用於動態場景之影像物件追蹤SoC系統設計, 智慧電子應用設計研討會, 2014/12/04, 智慧電子應用設計(IED)聯盟, 高雄市,高應大.
- 許明華, 2014, 低電壓且低功率之除 2 / 3 / 4 除頻器設計, 民生電子研討會, 2014/11/29, 東海大學電機工程學系、東海大學電子計算機中心、中華民國民生電子學會, 台中市,東海大學.
- 許明華, 2014, 新可調餘數模組{ 2n+k, 2n+1 – 1, 2n – 1}之低成本餘數反轉換器設計, 民生電子研討會, 2014/11/29, 東海大學電機工程學系、東海大學電子計算機中心、中華民國民生電子學會, 台中市,東海大學, pp.123-127.
- 許明華, 2014, 應用文理特徵之高效能影像除霧演算法, 國防科技學術研討會, 2014/11/14, 國防大學理工學院兵器系統中心, 桃園.
- 許明華, 2014, High Dynamic Range Image Based on Block-based Edge Strength for Embedded System Design, on Intelligent Information Hiding and Mulimedia Signal Processing IIHMSP-2014, 2014/08/27-29, IEEE Taiwan Section Taiwan Chapter of IEEE Signal Processing Society等, 日本,北九州市, pp.329-332.
- 許明華, 2014, Feature Points based Video Object Tracking for Dynamic Scenes and Its FPGA System Prototyping, on Intelligent Information Hiding and Mulimedia Signal Processing IIHMSP-2014, 2014/08/27-31, IEEE Taiwan Section Taiwan Chapter of IEEE Signal Processing Society等, 日本,北九州市, pp.325-328.
- 許明華, 2014, Ultra Low Power Circuit Design based on Adiabatic Logic, on Intelligent Information Hiding and Multimedia Signal Processing IIHMSP-2014, 2014/08/27-31, IEEE Taiwan Section Taiwan Chapter of IEEE Signal Processing Society等, 日本,北九州市, pp.317-320.
- 許明華, 2014, An Extensible VLSI Arcitecture for Parallel Label Merge in Multi-Pixel Image Processing, The 25th VLSI Design/CAD Symposium, 2014/08/05-08, 國立清華大學資工系/電機系/積體電路設計技術研發中心, 台中市,福容飯店.
- 許明華, 2013, 基於標籤再利用之快速影像物件標籤化演算法, 智慧電子應用設計研討會, 2013/12/13, 智慧電子應用設計聯盟, 台中市,勤益科大.
- 許明華, 2013, 基於區塊式邊緣強度之高品質曝光融合演算法與嵌入式系統設計, 智慧電子應用設計研討會, 2013/12/13, 智慧電子應用設計聯盟, 台市中,勤益科大.
- 許明華, 2013, 新3-餘數模組{22N-1, 2N+1, 2N-1}之低成本餘數反轉換器設計, 2013全國計算機會議, 2013/12/13-14, 教育部、亞洲大學, 台中市,亞洲大學.
- 許明華, 2013, THE FALL INCIDENT SURVEILLANCE SYSTEM DESIGN BASED ON HUMAN CONTOUR FEATURES, 2013全國計算機會議, 2013/12/13-14, 教育部、亞州大學, 台市中,亞州大學.
- 許明華, 2013, 新高效能3-餘數模組{2^(2N-1), 2^(N)-1, 2^(N-1)-1}之餘數轉二進轉換器, 2013民生電子研討會, 2013/11/22-23, 國立宜蘭大學電機資訊學院、中華民國民生電子學會, 宜蘭市,宜蘭大學.
- 許明華, 2013, FMCW雷達系統之嵌入式DSP設計與實現, 民生電子研討會, 2013/11/22-23, 國立宜蘭大學電機資訊學院、中華民國民生電子學會, 宜蘭市,宜蘭大學.
- 許明華, 2013, Fast Image Blending and Deghosting for Panoramic Video, Int. Conf. on Intelligent Information Hiding and Multimedia Signal Processing, 2013/10/15-18, 北京工業大學, 北京, pp.104-107.
- 許明華, 2013, A Computation Efficiency AND-CFAR for FMCW Radar Receiver, in Int. Conf. on Intelligent Information Hiding and Multimedia Signal Processing,, 2013/10/15-18, 北京工業大學, 北京.
- 許明華, 2013, Efficient Block-Based Dynamic Bbackground Modling and Foreground Object Detection in the DCT Domain, The Eighth International Conference on Innovative Computing, Information and Control (ICICIC2013), 2013/09/14-17, Tokai University, 熊本.
- 許明華, 2012, A Robust Background Modeling and Foreground Object Detection Using Color Component Analysis, 2012 IEEE Intl. Conf. on Systems, Man, and Cybernetics, 2012/10/14-17, IEEE SMC Society, Seoul, pp.263-267. (多色溫調變LED之智慧節能路燈系統研發-總計畫暨子計畫三:智慧型LED路燈控制)
- 許明華, 2012, Efficient Block-Based Foreground Detection for Outdoor Scenes on Embedded SoC Platforms, International Conference on Image, Vision and Computing, 2012/08/25-26, International Association of Computer Science & Information Technology, 上海, pp.21-25. (多色溫調變LED之智慧節能路燈系統研發-總計畫暨子計畫三:智慧型LED路燈控制)
- 許明華, 2012, Efficienct Block-Based Foreground Object Detection for Outdoor Scenes on Embedded SOC Platforms, Symposium on Digital life Technologies, 2012/08/15-16, 雲科大-資工系、自由軟體研究中心、成大數位生活科技研究中心, 雲林縣, pp.50-54. (多色溫調變LED之智慧節能路燈系統研發-總計畫暨子計畫三:智慧型LED路燈控制)
- 許明華, 2012, Fast Image Moving Object Segmentation Based on Block Texture for Embedded System Implementation, The 25th IPPR Conference on CVGIP, 2012/08/12-14, 中華民國影像處理與圖形識別學會, 南投縣. (多色溫調變LED之智慧節能路燈系統研發-總計畫暨子計畫三:智慧型LED路燈控制)
- 許明華, 2012, Intelligent Object Detection Implementation for Complex Scenes on an Embedded SoC Platform, The 23th VLSI Design/CAD Symposium,, 2012/08/07-10, 台灣大學電子所/電機系, 屏東. (多色溫調變LED之智慧節能路燈系統研發-總計畫暨子計畫三:智慧型LED路燈控制)
- 許明華, 2012, Region-based background subtraction for complex scene on embedded platforms, International Conf. on Intelligent Information Hiding and Multimedia Signal Processing, 2012/07/18-20, IEEE and the European Association for Biometrics, Piraeus-Athens, pp.351-34. (多色溫調變LED之智慧節能路燈系統研發-總計畫暨子計畫三:智慧型LED路燈控制)
- 許明華, 2011, New Reverse Converter Design of Moduli Set {2n, 2n+1-1, 2n-1}, International Conf. on Innovations in Bio-inspired Computing and Applications, 2011/12/16-18, 哈爾濱工業大學, 深圳, pp.201-204.
- 許明華, 2011, Effcient Color-Ingredient Particle Filter for Video Object Tracking, IEEE TENCON, 2011/11/21-23, Indonisia University, Bail,Indonisia, pp. 49-53. (國科會)
- 許明華, 2011, Pulse-Triggered Flip-Flop Design with PTL Style Control Scheme, IEEE TENCON, 2011/11/21-23, Indonisia University, Bali Island, pp.120-123. (國科會)
- 許明華, 2011, 高效能模組{2n, 22n-1, 22n-1-1}之餘數轉回二進制轉換器, 安全管理與工程技術國際研討會, 2011/11/17-18, 吳鳳科大, 嘉義,吳鳳科大, pp.51-54.
- 許明華, 2011, A Robust Object Detection Algorithm Using Multi-layer Background Model, The 24th IPPR Conf. on CVGIP, 2011/08/15-17, 高雄應用科大, 高雄,澄清湖, pp.121-124.
- 許明華, 2011, fficient Foreground Object Detection on Embedded Platform, The 22th VLSI Design/CAD Symposium, 2011/08/03-05, 中學大學, 雲林縣,古坑, pp.548-551.
- 許明華, 2010, FPGA Implementation for Image Object Detection System on NoCs, Asia Pacific Conf. on Circuits and Systems, 2010/12/06-09, IEEE Asia Pacific Conference on Circuits and Systems, 吉隆坡.
- 許明華, 2010, A Low Power Dual-Mode Pulse Triggered Flip-Flop Using Pass Transistor Logic, IEEE International Symposium on Next-Generation Electronics, 2010/11/18-19, IEEE, 國立中山大學, pp.203-206.
- 許明華, 2010, A Parallel Hardware Architecture for 4-Pixel Connected, Submit to 2010 International Conference on High-Speed Circuits Design (HSCD'10), 2010/10/28-29, 國立勤益科技大學, 台中市,勤益科技大學.
- 許明華, 2010, Efficient Multi-Layer Background Model on Complex Environment for Foreground Object Detection, 2010 Sixth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2010/10/15-17, IEEE, 達姆施塔特.
- 許明華, 2010, Fast Texture-Based Object Tracking Algorithm on Embedded Platform, The 5th international conference on Frontier of Computer Science and Technology, 2010/08/18-22, 吉林大學, 長春市,吉林大學, pp.643-646.
- 許明華, 2010, Efficient Multi-Layer Background Model on Complex Environment for foreground Object Detection, The 23th IPPR Conference on CVGIP, 2010/08/15-17, 中華民國影像處理與圖形識別學會,國立高雄大學, 高雄市.
- 許明華, 2010, 使用適應性背景模型於複雜場景中進行前景物件偵測, 第五屆智慧生活科技研討會, 2010/06/04, 琴益科技大學 資訊工程系(所), 台中縣,勤益科技大學, pp.1494-1498.
- 許明華, 2010, Low-voltage and low-power 10-transistor full adder design using degenerate logic module, the 5th intelligent living technology conference, 2010/06/04, 勤益科大, 台中縣,勤益科大.
- 許明華, 2009, Image Reconstruction by Convolution with Piecewise Linear Polynomal Kernel, Seventh International Conference on Information, Communications and Signal Processing, 2009/12/08-10, 南洋理工大學, 澳門.
- 許明華, 2009, A Micro-Network on Chip with 10-Gb/s Transmission Link, The attached file is a paper which is accepted by IEEE Asian Solid-State Circuits Conference 2009 (A-SSCC), 2009/11/16-18, 工研院, 台北, pp.277-280.
- 許明華, 2009, 即時多重影像物件追蹤與計數之嵌入式系統設計, 2009年雛型系統與電路設計創新應用研討會, 2009/10/16, 清雲科技大學, 清雲科技大學, pp.211-216.
- 許明華, 2009, Image Object Detection and Tracking Implementation for Outdoor Scenes on an Embedded SoC Platform, 2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2009/09/12-14, 國立高雄應用科技大學, 日本,京都, pp.386-389.
- 許明華, 2009, A Real-Time Architecture of Piecewise Linear Convolution Interpolation Kernel for Digital Image, The 22th IPPR Conference on CVGIP, 2009/08/23-25, 義守大學, 南投,溪頭, pp.825-830.
- 許明華, 2009, Image Object Detection and Tracking Implementation on An Embedded SoC Platform, The 22th IPPR Conference on CVGIP, 2009/08/23-25, 義守大學, 南投,溪頭, pp.873-878.
- 許明華, 2009, Parallel 3-Pixel Labeling Method and its Hardware Architecture Design, The Fifth International Conference on Information Assurance and Security (IAS-2009), 2009/08/18-20, 國立成功大學, 大陸,西安, pp.185-188.
- 許明華, 2009, The VLSI Architecture Design for 3-Pixel Labeling Approach, The 20th VLSI Design/CAD Symposium, 2009/08/04-07, 國立成功大學, 花蓮, pp.84.
- 許明華, 2009, A Novel Low Power Pulse-Triggered Flip-Flop Design with Pulse Width Control Scheme, The 20th VLSI Design/CAD Symposium, 2009/08/04-07, 國立成功大學, 花蓮.
- 許明華, 2009, Low-Power and Low-Complexity Dual-Mode Flip-Flop Design, 第四屆智慧生活科技研討會 (ILT2009), 2009/06/05, 國立勤益科技大學, 國立勤益科技大學.
- 許明華, 2009, Efficient VLSI Design of a Reverse RNS Converter for New Flexible 4-Moduli Set (2p+k, 2p+1, 2p-1, 22p+1), IEEE International Symposium on Circuit and System, 2009/05/24-27, 國立成功大學, 台北, pp.437-440.
- 許明華, 2008, Real-Time FPGA Architecture of Extended Linear Convolution for Digital Image Scaling, The2008 International Conference on Field-Programmable Technology, 2008/12/08-10, 台北.
- 許明華, 2008, Image Moving Object Segmentation and Tracking Based on Multi-Background Model, The 2008 Conference on Innovative Applocations of System Prototyping and Circuit Design, 2008/10/17, 台中, pp.141~146.
- 許明華, 2008, Area-Time-Power Efficient VLSI Design for Residue-to-Binary Converter based on Moduli Set (2^n,2^n+1-1,2^n-1), The 19th VLSI Design/CAD Symposium, 2008/08/05-08, 墾丁, pp.S16-6.
- 許明華, 2008, A VLSI Design on Novel Convolution Interpolation Kernel for Digital Image, The 19th VLSI Design/CAD Symposium, 2008/08/05-08, 墾丁, pp. S6-6.
- 許明華, 2008, Adaptive Motion Gesture Segmentation, IEEE International Conference on Embedded Software and Systems Symposia, 2008/07/29-31, 成都, pp.386-391.
- 許明華, 2008, A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing, IEEE International Conference on Embedded Software and Systems, 2008/07/29-31, 成都, pp.196-202.
- 許明華, 2008, The efficient VLSI Design of BI-Cubic Convolution Interpolation for Digital Image Processing, IEEE International Symposium on Circuit and System, 2008/05/18-21, 西雅圖, pp.480-483.
- 朱元昌, 陳嘉宏, 陳思穎, 蔡文凱, 許明華, 2007, 適應性動態手勢切割, 全國計算機會議, 2007/12/10-13, 台中, pp.53-62.
- Z.C. Wu, C.H. Chen, S.Y. Chen, C.C. Lin, W.K. Tsai, M.H. Sheu, 2007, The Efficient VLSI Design of Extended-Linear Scaling for Digital, National Computer Symposium, 2007/12/10-13, 台中, pp.83-92.
- C.C. Lin, Z.C. Wu, W.K. Tsai, M.H. Sheu and H.K. Chiang, 2007, The VLSI Design of Winscale for Digital Image Scaling, IEEE IIHMSP, 2007/11/26-28, 高雄, pp.511-514.
- S.H. Lin and M.H. Sheu, 2007, Low Power Multipliers Using Enhenced Row Bypassing Schemes, IEEE Workshop on Signal Processing System, 2007/10/17-19, 上海, pp.110-114.
- Y.T. Hwang, J.F. Lin, and M.H. Sheu, 2007, Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection, IEEE Workshop on Signal Processing System, 2007/10/17-19, 上海, pp.142-145.
- [11] 吳曾傳, 陳思穎, 林正基, 蔡文凱, 許明華, 2007, 高效能-BI-cubic之影像解析度縮放硬體實現, 系統雛型與電路設計創新應用研討會, 2007/10/02, 台南, pp.67-71.
- [7] J.F. Lin, S.W. Chin, Z.H. Ye, and M.H. Sheu, 2007, Low Power Multiplier Design Using Enhanced Column Bypassing Scheme, 2007系統雛型與電路設計創新應用研討會, 2007/10/02, 台南, pp.7-10.
- C.C. Lin, M.H. Sheu, H.K. Chiang, C. Liaw, and J.F. Lin, 2007, Motion Adaptive De-interlacing with Local Scene Changes Detection, IEEE International Conference on Innovative Computing Information and Control, 2007/09/05-08, 熊本, pp.142-145.
- C.C. Lin, M.H. Sheu, Z.C. Wu, and W.K. Tsai, 2007, The Efficient VLSI Design on BI-CUBIC Interpolation for Real Time Digital Image Scaling, The 16th VLSI Design/CAD Symposium, 2007/08/05-09, 花蓮, pp.2-6.
- S.H. Lin, M.H. Sheu, K.H. Wang, J.J. Zhu and S.Y. Chen, 2007, Novel VLSI Design of Circular-Carry-Select (CCS) Based Diminished-One Modulo 2n+1 Adde, The 16th VLSI Design/CAD Symposium, 2007/08/05-09, 花蓮, pp.a1-1.
- S.W. Yang, M.H. Sheu, C.K. Yeh, C.Y. Wen, C.C. Lin and W.K. Tsai, 2007, Fast Fair Crossbar Scheduler for On-Chip Router, IEEE International Symposium on Circuit and System, 2007/05/27-31, 紐奧良, pp.385-388. (經濟部)
- 林智傑, 葉正濠, 葉春楷, 溫智淵, 楊學雯, 許明華, 2007, 應用於晶片網路交換器之高效能仲裁器與交換電路控制架構, 智慧生活科技研討會, 2007/05/12, 台中, IC design.
- Y.T. Hwang, J.F. Lin, M.H. Sheu, and C.J. Sheu, 2006, Low Power Multiplier Designs Based on Improved Column Bypassing Schemes, IEEE Asia Pacific Conference on Circuits and Systems, 2006/12/04-07, 新加坡, pp.595-598.
- C.C. Lin, M.H. Sheu, H.K. Chiang, C.J. Wei, 2006, The VLSI Design of Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection, IEEE Asia Pacific Conference on Circuits and Systems, 2006/12/04-07, 新加坡, pp.1589-1592.
- S.H. Lin, M.H. Sheu, J.S. Lin, W.T. Sheu, 2006, Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2^n-1, 2^n+1, 2^(2n+1)), IEEE Asia Pacific Conference on Circuits and Systems, 2006/12/04-07, 新加坡, pp.2022-2025.
- J.C. Lee, S.W. Yang, and M.H. Sheu, 2006, VLSI Architecture for Multi-Minimum Sum of Square Error, 民生電子暨信號處理研討會, 2006/11/16, 新竹.
- J.F. Lin, Y.T. Hwang, M.H. Sheu, C.J. Sheu, and H.Y. Chen, 2006, Low Power Multiplier Designs Based on Improved Row & Column Bypassing Schemes, 民生電子暨信號處理研討會, 2006/11/16, 新竹.
- C.C Lin, M.H. Sheu, H. K. Chiang, C. L. and M.C. Chen, 2006, Film-to-Video Conversion with Scene Cut Detection, 2006 IEEE International Conference on Innovative Computing, Information and Control, 2006/08/30-2006/09/01, 北京, pp.285-288.
- J.F. Lin, Y.T. Hwang and M.H. Sheu, 2006, Low-Power and Low-Complexity Full Adder Design for Wireless Base and Applications, IEEE International Conference on Communication, Circuits and Systems, 2006/06/25-2006/07/01, 桂林, pp.2337-2341.
- Y.L. Lai, S.W. Yang, M.H. Sheu, Y.T. Hwang, H.Y. Tang, and P.Z. Huang, 2006, A High-Speed Network Interface Design for Packet-Based NoC, IEEE International Conference on Communication, Circuits and Systems, 2006/06/25-2006/07/01, 桂林, pp.2667-2671.
- 吳曾傳, 魏志任, 林正基, 楊學雯, 許明華, 2006, Winscale 演算法之影像解析度縮放硬體實現, 第一屆智慧生活科技研討會, 2006/06/09, 台中, pp.ICD-R10-95.
- 蔡文凱, 吳俊諺, 楊學雯, 林正基, 許明華, 2006, Hand Motion Image Detection for Gesture Recognition System, 第一屆智慧生活科技研討會, 2006/06/09, 台中, pp.ICS-R15-95.
- J.F. Lin, Y.T. Hwang, M.H. Sheu and C. C. Ho, 2006, A High Speed and Energy Efficient Full Adder Design Using Complementary & Level Restoring Carry Logic, IEEE International Symposium on Circuit and System, 2006/05/19-27, KOS, pp.2705-2708.
- C. C Lin, C. J. Wei, M.H. Sheu , H. K. Chishy and C. Liaw, 2006, The VLSI Design of De-interlacing with Scene Change Detection, IEEE International Symposium on Circuit and System, 2006/05/19-27, KOS, pp.2705-2708.
- C. C. Lin, M. H. Sheu, H. K. Chiang, C. S. Liaw, C. T. Tsai,, 2005, An Efficient Video De-interlacing with Scene Change Detection, IEEE Fifth International Conference on Information,Communications and Signal Processing, 2005/12/06-09, 泰國, pp. 36-40.
- 魏志任, 吳俊諺, 林正基, 許明華, 翁炳國, 巫穎毅, 2005, 考慮場景變化的解交錯演算法暨VLSI硬體實現, 2005年民生電子暨信號處理研討會, pp. O6-6.
- 鍾漢章, 吳光晃, 許明華, 翁炳國, 巫穎毅, 2005, 立體影像之邊緣適應性內插法與VLSI實現, 2005年民生電子暨信號處理研討會, pp. O15-1.
- 劉坤晏, 林蘇宏, 許明華, 郭源欽, 2005, 快速雙基底數碼轉換演算法與硬體設計, 2005年民生電子暨信號處理研討會, pp. O18-6.
- 吳俊諺, 蔡易霖, 楊學雯, 魏志任, 許明華, 2005, 車牌即時辨識之嵌入式軟硬體系統設計與實現, 2005年民生電子暨信號處理研討會, pp. 2-1.
- Y. L. Lai, S. W. Yang, M. H. Sheu, Y. T. Hwang, H. Y. Tang, and P. Z. Huang, 2005, A High-Speed Network Interface Design for Packet-Based NoC, Workshop on Consumer Electronics and Signal Processing, pp. 1-8.
- C. C. Lin, M. H. Sheu, H. K. Chiang and C. Liaw, 2005, Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection, The 6th Pacific Rim Conference on Multimedia, 2005/11/13-16, 韓國, pp. 291-302.
- S. H. Lin, M. H. Sheu, J. S. Lin and W. T., Sheu, 2005, Efficient VLSI Design for Reverse RNS Converter Based on New Moduli Set (2^n-1,2^n+1,2^(2n+1)), The 16th VLSI Design/CAD Symposium, 2005/08/09-12, Taiwan.
- S. W. Yang, M. H. Sheu, H. H. Wu, H. E. Chien, P. K. Weng, and Y. Y. Wu, 2005, VLSI Architecture Design for a Fast Parallel Label Assignment in Binary Image, IEEE International Symposium on Circuits and Systems, 2005/05/22-26, Kobe, pp. 2393-2396.
- H. H. Wu, M. H. Sheu, T. Y. Yang,, 2005, Directional Interpolation for Field-Sequential Stereoscopic Video, IEEE International Symposium on Circuits and Systems, 2005/05/22-26, Kobe, pp. 2879-2882.
- 洪俊傑, 賴永隆, 許明華, 方喬立, 2004, 具時脈抖動自我測試之鎖相迴路設計, 2004年大學發展與產學合作-大學校院學術論文發表暨研討會, 2004/12/12, 斗六, pp. B-15.
- 洪俊傑, 賴永隆, 許明華, 方喬立, 2004, 光學滑鼠七位元類比數位轉換器之低成本與低功率電路與佈局設計, 2004年大學發展與產學合作-大學校院學術論文發表暨研討會, 2004/12/12, 斗六, pp. B-9.
- S. H. Lin, M. H. Sheu and S. W. Yang, 2004, Efficient VLSI Architecture Design for Complex Linear Convolution Using Conjugate-Polynomial-Channel Residue Arithmetic System, IEEE APCAS, 2004/12/10-14, Tainan, pp. 829-834.
- M. H. Sheu S. H. Lin, Y. T. Chen, and Yu-Chun Chang, 2004, Low-Cost and High-Speed RNS Forward Converter for the (2^n-1,2^n,2^n+1) Moduli Set, IEEE APCAS., 2004/12/10-14, Tainan.
- M. H. Sheu S. H. Lin, Y. T. Chen, and Y. C. Chang, 2004, High-Speed and Reduced-Area RNS Forward Converter Based on (2^n-1, 2^n, 2^n+1) Moduli Set, The 15th VLSI Design/CAD Symposium, 2004/08/15-18, 墾丁, pp.4-17.
- S. H. Lin, M. H. Sheu and S. W. Yang, 2004, Efficient VLSI Architecture for Complex Linear Convolution Using Conjugate-Polynomial-Channel Residue Arithmetic System, The 15th VLSI Design/CAD Symposium, 2004/08/15-18, 墾丁, pp.C2-6.
- S. H. Lin, M. H. Sheu and S. W. Yang, 2003, Efficient VLSI Implementation for Residue to Binary Converter Based on a Balance Moduli Set (2^n-3, 2^n+1, 2^n-1, 2^n+3), IEEE International Conf. on Informatics, Cybernetics and Systems, 2003/11/01-03, 高雄, pp. 313-318.
- C. Chen, R. L. Chen and M. H. Sheu,, 2003, A fast additive normalization method for exponential computation, Proceedings of Euromicro Symposium on Digital System Design, 2003/09/11-13, 安卡拉.
- Y. T. Shih and M. H. Sheu, 2003, A Low Cost Direct Digital Frequency Synthesizer Based on Recursive Trigonometric Approach, The 14th VLSI Design/CAD Symposium, 2003/08/15-18, Hualien, pp. 413-416.
- J. C. Hsu, M. H. Sheu, S. F. Tsai and C. H. Liu, 2003, An ASIC Design for Radar Baseband Detector, 航空電子科技與應用研討會, 2003/05/12-15, 高雄, pp. A2-33.
- M. H. Sheu and S. H. Lin, 2002, Fast Design Approach for Implementing the Approximate Squaring Function, IEEE Asia-Pacific Conference on Circuits and Systems, 2002/11/09-13, pp. 25-29.
- M. H. Sheu, S. H. Lin and S. W. Yang, 2002, An Efficient VLSI Implementation of Residue to Binary Converter for Specific Moduli (2^n-3,2^n+1,2^n-1,2^n+3), The 13th VLSI Design/CAD Symposium, 2002/08/16-19, 花蓮, pp. 383-387.
- S.T. Kan, J.F. Shiau, M.H. Sheu, and H.E. Liao, 2001, A Low-Cost VLSI Architecture Design with Cascaded Filter for Frequency-Detection, 12th VLSI Design/CAD Symposium, Hsinchu, pp. C2-11.
- S.H. Lin and M.H. Sheu, 2001, Fast Compensative Approach for Hardware Implementation of Approximate Squaring Function, The 12th VLSI Design/CAD Symposium, Hsinchu, pp. C1-2.
- C. M. Wu, M. D. Shieh, C. H. Wu and M. H. Sheu, 2001, VLSI Architecture of Extended In-Place Path Metric Update for Viterbi Decoders, IEEE International Symposium on Circuits and Systems, pp. 446-449.
- M.H. Sheu, H.E. Liao, S.T. Kan, and M.D. Shieh, 2001, A Novel Adaptive Algorithm and VLSI Design for Frequency Detection In Noisy Environment Based on Adaptive IIR Filter, IEEE International Symposium on Circuits and Systems May.
- S. S. Yang and M. H. Sheu, 2000, Chaotic Competitive Hopfield Neural Network for Medical Image Segmentation, 2000 Conference on Engineering Technology and Applications to Chinese and Western Medicine, pp. 177-184.
- M. H. Sheu, S. S. Yang, and K. Y. Lin, 2000, A Novel Algorithm and VLSI Design of Fast Stabilized Cascade Adaptive Filter for Frequency-Detection, The 11th VLSI/CAD Symposium, pp. 307-310.
- M. H. Sheu, S. J. Jiang, and C. C. Kuo, Aug., 2000, VLSI Architecture Design for Class-of-Service Packet Scheduling, The 11th VLSI/CAD Symposium, pp. 221-224.
- M. H. Sheu and S. T. Kan, 2000, A VLSI Design for Single Sinusoidal Frequency Detection in Noisy Environment, Workshop on Consumer Electronics, pp. 452-456.
- M. D. Shieh, C. H. Wu, M. H. Sheu, J. L. Sheu, and C. H. Wu, 2000, Asynchronous Implementation of Modular Exponentiation for RSA Cryptography, The 2st Asia-Pacific Conference on ASIC, pp. 123-126.
- H. E. Liao, M. H. Sheu, and S. S. Yang, Aug., 2000, A New VLSI Design for Adaptive Frequency-Detection Based on the Active Oscillator, The 2st Asia-Pacific Conference on ASIC, pp. 123-126.
- C.C. Wang, M. H. Sheu, and H.E. Liao, 2000, An Efficient VLSI Design of Adaptive IIR Filter for Frequency Detection, Proceedings of the Fifth Symposium on Computer & Communication Technology, pp. 4B21-4B25.
- M. H. Sheu, S. J. Jiang and C. C. Kuo, 2000, Architecture Design for Class-of-Service Packet Scheduling, The 11th VLSI/CAD Symposium, 2000/08/12-16, 墾丁, pp.221-224.
- 許明華, 林銘華, 楊士賢, 林灶生, 林基源, 1999, A Modified Competitive Learning Network inImage Compression and VLSI Implementation, 第 15 屆全國技職研討會研討會, pp. 189-198.
- M. H. Sheu and S. C. Tsai, 1999, A Lossless Index Coding Algorithm and VLSI Design for Vector Quantization, The 10th VLSI/CAD Symposium, pp. 485-488.
- M. D. Shieh, C. H. Wu, M. H. Sheu, and C. H. Wu., 1999, A VLSI Architecture of Fast High-Radix Modular Multiplication for RSA Cryptosystem, IEEE International Symposium on Circuits and Systems.
- 許明華, 王瑞欽, 吳鴻武, 郭文杰, 1998, 乙太網路媒介擷取控制之超大型積體電路設計, 第 4 屆電腦與通訊研討會, pp. 99-102.
- M. H. Sheu, M. D. Shieh, and S. W. Sheng, 1998, A VLSI Architecture Design with Lower Hardware Cost and Less Memory for Separable 2-D Discrete Wavelet Transform, IEEE International Symposium on Circuits and Systems May, pp. 449-452.
- M. D. Shieh, M. H. Sheu, C. M. Wu, and W. S. Ju, 1998, Efficient Management of In-Place Path and Its Implementation for Viterbi Decoders, IEEE International Symposium on Circuits and Systems May, pp. 457-460.
- J. L. Sheu, M. D. Shieh, C. H. Wu, and M. H. Sheu, 1998, A Pipelined Architecture of Fast Modular Multiplication for RSA Cryptography, IEEE International Symposium on Circuits and Systems May, pp. 121-124.
- C. H. Chen, M. H. Sheu, M. D. Shieh, T. S. Li, and M. T. Chen, 1998, Design and Implementation of a 10/100 Mbps Ethernet Switching Hub Controller, IEEE Asia Pacific Conference on Communications.
- M. H. Sheu and C. L. Chang, 1998, An Efficient VLSI Architecture Design for Fast Vector Quatization, The 9th VLSI/CAD Symposium, pp. 485-488.
- M. H. Sheu, Chung-Ho Chen, and Tzung-Shiue Li, 1998, The Shared Bus Architecture Design and Chip Implementation for 10M/100Mbps Ethernet Switching Fabric, IEEE International Conference on Consumer Electronics, pp. 250-253.
- 林修民, 蔡世祺, 許明華, 1997, 實用自動販賣機控制器之特殊用途積體電路設計, 第 12 屆全國技職研討會, pp. 56-59.
- W.S. Ju, M.D. Shieh, and M.H. Sheu, 1997, A Low-Power VLSI Architecture for the Viterbi Decoder, IEEE 40th Midwest Symposium on Circuit and Systems.
- M.H. Sheu, M.D. Shieh, S.W. Liu, and C. Dou, 1997, An Efficient Hardware Design Approach from System-Level Specification, IEEE 40th Midwest Symposium on Circuit and Systems.
- M.H. Sheu, M.D. Shieh, and S.W. Liu, 1997, A Low-Cost VLSI Architecture Design for Non-Speparable 2-D Discrete Wavelet Transform, IEEE 40th Midwest Symposium on Circuit and Systems.
- M.H. Sheu, M.D. Shieh, and S.W Liu, 1997, An Efficient VLSI Architecture Design for Separable 2-D Discrete Wavelet Tansform, The 8th VLSI Design/CAD Symposium, pp. 121-124.
- M.D. Shieh, M.H. Sheu, and Y.C. Hsu, 1997, A High-Performance VLSI Architecture for Maps Criterion Motion Estimation, IEEE 40th Midwest Symposium on Circuit and Systems.
- C. Dou, M.D. Shieh, and M.H. Sheu, 1997, Performance Evaluation for HW/SW Codesign of Communication Protocls, Asia-Pacific Conference on Hardware Description Language.
- 蘇文林, 莊盈洲, 塗正宗, 許明華, 1996, 影像移動估算之平均絕對差值積體電路設計, 第 11 屆全國技職研討會, pp. 177-182.
- 黃聰琦, 卓進豐, 許明華, 1996, 一適用波元轉換之捲積運算模組晶片設計, 第 11 屆全國技職研討會, pp. 505-510.
- Ming-Der Shieh, Wann-Shyang Ju, and M.H. Sheu, 1996, Low-Power State Assignment for Asynchronous Finite State Machines, IEEE 39th Midwest Symposium on Circuit and Systems, pp. 1325-1328.
- Ming-Der Shieh, M.H. Sheu, and Yu-Chin Hsu, 1996, MAPS: A New Efficient Block-Matching Criterion for Motion Estimation, IEEE 39th Midwest Symposium on Circuit and Systems, pp. 1393-1396.
- M.H. Sheu, S.F. Cheng, and M.D. Shieh, 1996, A Pipelined VLSI with Module Structure Design for Discrete Wavelet Transforms, IEEE International Symposium on Circuits and Systems May, pp. 352-355.
- M.H. Sheu, M.D. Shieh, S.W. Liu, and C. Dou, 1996, A New System - Level Design Approach by Mapping Graphic SDL to VHDL, The 7th VLSI Design/CAD Symposium Proceeding, pp. 171-174.
- M.H. Sheu, M.D. Shieh, and S.F. Cheng, 1996, A Unified VLSI Architecture for Decomposition and Synthesis of Discrete Wavelet Transform, IEEE 39th Midwest Symposium on Circuit and Systems, pp. 113-116.
- M.H. Sheu and H.Y. Lee, 1996, Subband Coding 之探討及 VLSI 設計製作, The Second Symposium on Computer and Communication Technology, pp. 129-138.
- M.D. Shieh, M.H. Sheu, H.R. Wang, and H.C. Cheng, 1996, Reducing the Switching Activity in Asynchronous Circuits for Low Power Dissipation, The 7th VLSI Design/CAD Symposium Proceeding, pp. 165-168.
- M.D. Shieh, J.M. Horng, and M.H. Sheu, 1996, A CAD System for Autmatic Synthesis of Generalized Asynchronous Circuits, IEEE International Symposium on Circuits and Systems May, pp. 818-821.
- M. D. Shieh, M. H. Sheu, , and Y. C. Hsu, 1996, An Efficient Block-Matching Criterion and Its VLSI Implementation for Motion Estimation, The Second Symposium on Computer and Communication Technology, pp. 122-128.
- Hong-Yeong Lee, Leu-Shing Lan, M.H. Sheu, and Chien-Hsing Wu, 1996, A Parallel Architecture for Arithmetic Coding and Its VLSI Implementation, IEEE 39th Midwest Symposium on Circuit and Systems, pp. 1309-1312.
- M.H. Sheu, Y.C. Hsu, and M.D. Shieh, 1995, A High Performance VLSI Architecture for the Full Search Block Matching Algorithm, The 1st Symposium on Computer and Communication Technology, pp. 149-153.
- M.H. Sheu, S.F. Cheng, and M.D. Shieh, 1995, A Pipelined VLSI Architecture for Discrete Wavelet Transform, The 6th VLSI Design/CAD Symposium Proceeding, pp. 199-202.
- M.D. Shieh, J.M. Horng, and M.H. Sheu, 1995, Automating the design of Generalized Asynchronous Circuits From High-Level Specification, The 6th VLSI Design/CAD Symposium Proceeding, pp. 290-293.
- M.D.Shieh, S.F.Cheng, and M.H.Sheu, 1995, Automating the Design of Generalized Asynchronous Circuits From High-Level Specifications, The 6th VLSI Design/CAD Symposium Proceeding, 1995/08/13-17, 瑞里, pp.290-293.
- M.H. Sheu, J.F.Wang, and J.Y.Lee, 1993, An Architecture with Low Memory-Bandwidth and Hardware Cost for 3-Step Block Matching Algorithm, IEEE TENCON, Beijing, pp. 559-562.
- M.H. Sheu, J.F. Wang, L.Y. Liu, and J.Y. Lee, 1993, An Expandable Chip Design for Gray-Scale Morphological Operations, IEEE International Symposium on Circuits and Systems, Chicago.
- M.H. Sheu, J.F. Wang, and J.Y. Lee, 1993, A High Throughput-Rate Architecture for 8*8 2-D DCT, IEEE International Symposium on Circuits and Systems, Chicago.
- M.H.Sheu, J.F.Wang, and J.Y.Lee, 1993, An Expandable Chip Design for Gray-Scale Morphological, IEEE International Symposium on Circuits and Systems, 1993/05/19, Chicago.
- L.Y. Liu, J.F. Wang, J.Y. Lee, and M.H. Sheu, 1992, A New Approach for Operation Scheduling with Data Flow Graph Reforming, International Symposium on Circuits and Systems, pp. 1941-1944.
- J.F. Wang, L.Y. Liu, C.H. Cheng, M.H. Sheu, Y.L.Jeang and Y.L. Lee, 1992, An ASIC Design for Linear Predictive Coding of Speech Signals, Proceedings of EURO ASIC, pp. 288-293.
- M.H. Sheu, J.F. Wang, G.R. Liang and J.Y. Lee, 1991, VLSI Implementation of Testable Chip: LPC-T, International Symposium on Communication.
- J.F. Wang, M.H. Sheu, J.L. leang, W.Y. Lee and J.Y. Lee, 1990, A New Synthesis of Microprogrammed Controllers for Multicycling Operation, International Computer Symposium, pp. 712-717.
- 蔣元隆, 王駿發, 許明華, 李肇嚴, 1989, 一個最佳化暫存器全域配置演算法, 第 4 屆技術及職業教育研討會, pp. 4081-4092.
- J.F. Wang, Y.L. Jeang, M.H. Sheu, and J.Y. Lee, 1989, On the Register Allocation and Algorithms, International Symposium on VLSI Technology,Systems and Applications, pp. 126-128.
- J.F. Wang, L.Y. Jeang, M.H. Sheu, and J.Y. Lee, 1989, CKU-RA: A Problem for Optimal Register Allocation, Proceedings of National Computer Symposium, pp. 126-135.
三、技術報告- 許明華, 吳先晃, 2006, 小型都卜勒雷達後級訊號處理多用途晶片縮裝設計, 中山科學研究院. (執行期間:2006年1月1日至2006年12月31日)
- 許明華, 吳先晃, 2005, 即時影像物件偵測之數位矽智產設計與實現研究, 中山科學研究院. (執行期間:2005年1月1日至2005年12月31日)
- 許明華, 吳先晃, 2004, 影像移動處理演算法與DSP ASIC開發, 中山科學研究院. (執行期間:2004年1月1日至2004年12月31日)
- 許明華, 王文魁, 洪俊傑, 方喬立, 2004, 光學滑鼠七位元類比數位轉換器之低成本與低功率電路與佈局設計, 國科會. (執行期間:2003年8月1日至2004年7月31日)
- 許明華, 吳先晃, 2003, 小型都卜勒雷達後級訊號處理電路之ASIC縮裝設計, 中山科學研究院. (執行期間:2003年1月1日至2004年12月31日)
- 許明華, 王文魁, 黃新武, 楊學雯, 2003, 光學滑鼠控制系統單晶片設計, 國科會. (執行期間:2002年8月1日至2003年7月31日)
- 許明華,, 2002, 數位矽智產設計導論—FPGA Synthesis and Prototyping Design, 教育部. (執行期間:2002年1月1日至12月31日)
- 許明華, 謝明得, 郭家城, 王朝琴, 2001, The Design of Partial Memory Engine version 7 ASIC, 毓發科技公司. (執行期間:2001年1月1日至2001年12月31日)
- 許明華, 2001, 微電子快速雛型系統製作實習教材, 教育部. (執行期間:2001年1月1日至2001年12月31日)
- 許明華, 1997, 快述離散波元轉換之超大型積體電路設計與信號處理應用的研究, 國科會. (執行期間:1996年8月1日至1997年7月)
- 許明華, 1997, 硬體描述語言與模擬實習教材大綱, 教育部. (執行期間:1996年8月1日至1997年7月31日)
- Sheu, M. H., M.D.Shieh and C. Dou,, 1996, SDL 與VHDL之軟體與硬體整合設計研究, 國科會. (執行期間:1995年8月1日至1996年7月31日)
- 許明華, 1995, 進階超大型積體電路系統之工程教育改進, 國科會. (執行期間:1994年8月1日至1995年7月31日)
四、其他論著- M.H. Sheu, 1993, A Study on High-Level Synthesis and Chip Design, Ph.d. Dissertation, National Cheng Kung University.
- M.H. Sheu, 1989, Global Optimal Register Allocation in Digital System, Master Thesis, National Cheng Kung University.
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