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         西元      
楊博惠老師的論文著述

一、學術期刊論文

  1. 楊博惠, 2011, Cost-effective Variable Node Using Thermalcode Addition for LDPC Decoders, IEICE Electronics Express, Vol.8, pp.1948-1953. (SCI)
  2. 楊博惠, 2009, A Concise Min-Sum LDPC Decoder Using Simplified Comparators, International Journal of Electrical Engineering, Vol.16, No.6, pp.473-478. (EI)(97-2220-E-224-001)
  3. 楊博惠, 2009, A Low-Complexity and High-Performance 2D Look-up Table for LDPC Hardware Implementation, IEICE Fundamentals, Vol.92-A, No.11, pp.2941-2944. (SCI)(96-2221-E-224-079)
  4. P.-H. Yang and J. S. Wang, 2002, Design of Low-Voltage CMOS Pulsewidth Control Loops for SoC Applications. (SCI)
  5. Jinn-Shyan Wang, Shang-Jyh Shieh, Jei-Chien Wang and Po-Hui Yang, 2001, The design of a standard cell library for low-power / low-voltage VLSI applications. (SCI)
  6. Jinn-Shyan Wang and Po-Hui Yang, 2001, A Low-Voltage CMOS Pulsewidth Control Loop Using a Push-Pull Charge Pump. (SCI)
  7. Jinn-Shyan Wang, Po-Hui Yang and Duo Sheng, 2000, Design of a 3-V 300-MHz low-power 8 x 8-bit pipelined multiplier using pulse-triggered TSPC flip-flops. (SCI)
二、研討會論文
  1. Po-Hui Yang, Jing-Min Chen, Ching-Ken Chen, 2015, A Temperature Sensor Cell Design with System in Pakage Application, The 4th International Conference on Frontier Computing (FC 2015), 2015/09/09-11, IET, Bangkok, pp.626-631.
  2. Po-Hui Yang, Jing-Min Chen, Zi-Min Hong, 2015, All-digital High-Speed Wide-Range Binary Detecting Pulse-Width Lock Loops, The 4th International Conference on Frontier Computing (FC 2015), 2015/09/09-11, IET, Bangkok, pp.619-625.
  3. Po-Hui Yang, Jing-Min Chen, Po-Yu Kuo, Chia-Chun Wu, 2015, Application on Metastable Measurementwith Wide Range High Resolution VDL Circuit, WASET, International Conference on Electrical Engineering and Technology 2015., 2015/05/28-29, World Academy of Science, Engineering and Technology, Tokyo, pp.3233-3236.
  4. 楊博惠, 2012, A Light input Loading High-Speed Differential D Flip-Flop, The 2nd Conference on Applications of Innovation & Invention, 2012/11/23-24, 勤益科大, 台中市,勤益科大.
  5. 楊博惠, 2012, A Wide Range and High Resolution Vernier Delay Line for Metastability Measurement Applications, The 2nd Conference on Applications of Innovation & Invention, 2012/11/23-24, 勤益科大, 台中市、勤益科大.
  6. 楊博惠, 2012, A High-Performance 128-to-1 CMOS Multiplexer Tree, 2012 Intelligent Signal Processing and Communication Systems, 2012/11/05-07, IEEE, 新北市,淡江大學.
  7. 楊博惠, 2012, The Analysis and Improvement of Metastability in Basic Feedback-connected Logic Circuit, The 7th Intelligent Living Technology Conference, 2012/06/01-02, 勤益科大, 台中市,勤益科大.
  8. 楊博惠, 2012, A High-Speed CMOS Many-to-One Multiplexer Design, The 7th Intelligent Living Technology Conference, 2012/06/01-02, 勤益科大, 台中市,勤益科大.
  9. 楊博惠, 2012, Embedded Ring Oscillator Based Low Error Temperature Sensor Design, The 7th Intelligent Living Technology Conference, 2012/06/01-02, 勤益科大, 台中市,勤益科大.
  10. 楊博惠, 2012, A Fast Wake-up Power Gating Technique with Inducing A Balanced Rush Current, 2012 International Symposium on Circuits and Systems, 2012/05/20-23, IEEE, 首爾.
  11. 楊博惠, 2011, A Voltage Fluctuation Immunity Standard Cell Based Temperature Sensor, The 1st Conference on Applications of Innovation & Invention, 2011/11/24-25, 勤益科大, 台中市,勤益科大, pp.274-278.
  12. 楊博惠, 2011, A Fast Single Delay Line Pulsewidth Lock Loops, The 1st Conference on Applications of Innovation & Invention, 2011/11/24-25, 勤益科大, 台中市,勤益科大, pp.310-313.
  13. 楊博惠, 2011, The Analysis and Improvement of Metastability in Basic Feedback-connected Logic Circuits, The 1st Conference on Applications of Innovation & Invention, 2011/11/24-25, 勤益科大, 台中市,勤益科大, pp.314-318.
  14. Cheng-Chung Liao, Chao-Ching Tang and Po-Hui Yang, 2010, An Analysis of Metastability in High-Speed D-Flip Flops, 2010 International Conference on High-Speed Circuits Design (HSCD' 10), 2010/10/28-29, 勤益科大, 台中市,勤益科大, pp.75-80.
  15. Yao-Sian Su, Ming-Xian Liu and Po-Hui Yang, 2010, A Parallel Connection Embedded All Digital Temperature Sensing System Design, International Conference on High-Speed Circuits Design (HSCD'10), 2010/10/28-29, 勤益科大電子系, 台中市,勤益科大, pp.69-74. (98-2221-E-224-053-)
  16. 魏劭全, 楊博惠, 2010, A Parallel CORDIC Using Array Double Update Technique for QR Decomposition Hardware Implementation, 2010 Conference on Innovative Applications of System Prototyping and Circuits Design, 2010/10/15, 清雲科技大學, 桃園縣,清雲科大, pp.182-186.
  17. 吳星儀, 連振凱, 楊博惠, 2010, Prototyping Design for Lower PAPR Computational Complexity for OFDM System, 2010 Conference on Innovative Applications of System Prototyping and Circuits Design, 2010/10/15, 清雲科技大學, 桃園縣,清雲科大, pp.138-142.
  18. Jia-Ping Liu, Sing-Yi Wu, and Po-Hui Yang, 2010, A Low Cost Variable Node Using Thermalcode Addition for LDPC Decoder, 2010 VLSI Design/CAD Symposium, 2010/08/03-06, 成功大學, 高雄, pp.655-658.
  19. Ming-Jen Chen, Yi-Mao Hsiao, Yuan-Sun Chu and Po-Hui Yang, 2010, Documents Relationship Creation with Vocabulary Probability Analysis, 2010 International Conference on Information and Communication Technologies, 2010/05/25-29, World Academy of Science, Engineering and Technology, Tokyo, Narita, pp.79-82.
  20. 楊博惠, 2009, Embedded All Digital Temperature Sensor, 2009 Conference on Innovative Applications of System Prototyping and Circuits Design, 2009/10/16, 清雲科技大學, 桃園,清雲科技大學. (嵌入式系統晶片之多點溫度感測電路設計研究)
  21. 楊博惠, 2009, All Digital Wide Rang Cyclic Sampling Pulsewidth Lock Loops, 2009 Conference on Innovative Applications of System Prototyping and Circuits Design, 2009/10/16, 清雲科技大學, 桃園,清雲科技大學. (嵌入式系統晶片之多點溫度感測電路設計研究)
  22. 楊博惠, 2009, A Recyclable Detection All Digital Pulsewidth Locked Loops, 2009 International Conference on High-Speed Circuit Design, 2009/10/04-07, 聖約翰科技大學, 台北縣,聖約翰科技大學. (嵌入式系統晶片之多點溫度感測電路設計研究)
  23. 楊博惠, 2009, A Low-Cost AND Operation Min-Sum Algorithm LDPC Decoder for IEEE 802.16e Application, 2009 VLSI Design / CAD Symposium, 2009/08/04-07, 國立中正大學, 花蓮. (MIMO傳送式之多畫面智慧型視訊安全監視系統研究)
  24. Po-Hui Yang; Jung-Chieh Chen; Ya-Ting Chan; Ming-Yu Lin, 2008, A Simplified Addition Operation Log-SPA LDPC Decoder, The 14th Asia-Pacific Conference on Communications, 2008/10/14-16, 東京.
  25. Po-Hui Yang; Ming-Jau shiau; Cheng-His Tsai, 2008, An All Digital Pulsewidth Locked Loops Using Recyclable Detection Technique, 2008 Asia-Pacific Chinese Conference on High-Speed Circiut Design (HSCD'08), 2008/07/22-23, 台北縣.
  26. Po-Hui Yang; Chun-Hung Lin; Kuen-Ru Tsai, 2008, An All Digital Embbed Multi-point Temperature Sensor System for SoC Applications, 2008 Asia-Pacific Chinese Conference on High-Speed Circiut Design (HSCD'08), 2008/07/22-23, 台北縣.
  27. Po-Hui Yang; Ming-Jau shiau; Cheng-His Tsai ; Jia-Shuo Liang, 2007, A Low- Power Embedded All Digital Temperature Sensor, 2007 Conference on Innovative Applications of System Prototyping and Circuit Design, 2007/09/28, 台南.
  28. Po-Hui Yang; Chun-Hung Lin; Kuen-Ru Tsai, 2007, Wide Frequency Range High-Speed All Digital Pulsewidth Locked Loops, 2007 Conference on Innovative Applications of System Prototyping and Circuit Design, 2007/09/28, 台南.
  29. 楊博惠, 2007, A low-Power Embedded All Digital Temperature Sensor, 2007 Conference on Innovative Applications of System Prototyping and Circuits Design, 2007/09/28, 台南市.
  30. 楊博惠, 2007, A New High-Speed Counter Based Viterbi Decoder, 2007 Conference on Innovative Applications of System Prototyping and Circuits Design, 2007/09/28, 台南市.
  31. 楊博惠, 2007, Wide Frequency Range High-Speed All Digital Pulsewidth Locked Loops, 2007 Conference on Innovative Applications of System Prototyping and Circuits Design, 2007/09/28, 台南市.
  32. 楊博惠, 2007, A Low-Complexity High-Performance Two-DimensionalLook-Up Table for LDPC Hardware Implementation, 2007 VLSI/CAD Symposium, 2007/08/07-10, 花蓮.
  33. 楊博惠, 2007, A Low-Hardware-Cost Logical OR Operation Log-SPA LDPC Decoder, 2007 VLSI/CAD Symposium, 2007/08/07-10, 花蓮.
  34. 楊博惠, 2006, 2006 Conference on Electronic Communication and Applications, A New High Speed Low Power Counter Based Viterbi Decoder, 2006/07/06, 高雄市, pp.175-178. (NSC95-2221-E-224-101)
  35. 賴義澤, 廖健棠, 楊博惠, 2006, 2006 Conference on Electronic Communication and Applications, A High-Bit Clear Normalization Technique for High-Speed and Low-Power Viterbi Decoder, 2006/07/06, 高雄市, pp.196-200. (NSC95-2221-E-224-101)
  36. Shuenn-Yuh Lee; Yueh-Lun Tsai; Wei-Zen Su; Po-Hui Yang, 2003, A 2.5 V switched-current sigma-delta modulator with a novel class AB memory cell.
  37. Po-Hui Yang, Jinn-Shyan Wang and Yi-Ming Wang, 2000, A 1-GHz low-power transposition memory using new pulse-clocked D flip-flops.
  38. Jinn-Shyan Wang; Po-Hui Yang, 2000, Power analysis and implementation of a low-power 300-MHz 8-b x 8-b pipelined multiplier.
  39. Jinn-Shyan Wang, Po-Hui Yang and Tseng, W., 1998, Low-power embedded SRAM macros with current-mode read/write operations.
  40. Jinn-Shyan Wang and Po-Hui Yang, 1998, A pulse-triggered TSPC flip-flop for high-speed low-power VLSI design applications.
三、技術報告
  1. 楊博惠, 2013, 無線通訊系統之低密度奇偶校驗碼低成本積體電路設計技術及其雛型系統建構. (執行期間:2008年05月01至2013年04月31日)
 
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