一、學術期刊論文

1. Hwang C.-S.*, T.-L. Chu and Y.-G. Chen, 2018, Divider-less SAR-based ADDLL, IET-Electronics Letters, Vol.54, No.2, pp.62-64. (EI, SCIE)
2. Chen C.-C.*, C.-S. Hwang, Y. Lin and G.-H. Chen, 2016, All-Digital Pulse-Shrinking Time-to-Digital Converter with Improved Dynamic Range, Review of Scientific Instruments, Vol.87, No.4, pp.046104(1-3). (SCI, EI)
3. Chen C.-C.*, C.-S. Hwang, Y.-T. Lin and K.-C. Liu, 2015, All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters, Review of Scientific Instruments, Vol.86, No.12, pp.126113(1-3). (SCI)
4. Chen C-C., C.-S. Hwang, K.-C. Liu, G.-H. Chen, 2014, CMOS Time-to-Digital Converter Based on a Pulse-Mixing Scheme, Review of Scientific Instruments, Vol.85, No.11, pp.114702(1-9). (SCI, EI)
5. Chen, C.-C., S.-H. Lin and C.-S. Hwang, 2014, An Area-Efficient CMOS Time-to-Digital Converter Based on a Pulse-Shrinking Scheme, IEEE Transactions on Circuits and Systems II: Express, Vol.61, No.3, pp.163-167. (SCI, EI)
6. Mao, W.-L., J.-S. Du, J. Sheen and C.-S. Hwang, 2013, Adaptive multipath mitigation tracking system for GPS receiver, Aerospace Science and Technology, Vol.30, No.1, pp.66-78. (SCI)
7. Chen Y.-G., H.-W. Tsao and C.-S. Hwang*, 2013, A Fast-Locking All-Digital Deskew Buffer with Duty-Cycle Correction, IEEE Transactions on Very Large Scale Integration Systems, Vol.21, No.2, pp.270-280. (SCI, EI)
8. Chen C.-C., P. Chen, C.-S. Hwang and W. Chang, 2005, A precise cyclic CMOS time-to-digital converter with low thermal sensitivity, IEEE Transactions on Nuclear Science, Vol. 51, No. 4, pp. 834-838. (SCI, EI)
9. Hwang C.-S., P. Chen and H.-W. Tsao, 2004, A high-precision time-to-digital converter using a two-level conversion scheme, IEEE Transactions on Nuclear Science, Vol. 51, No. 4, pp. 1349-1352. (SCI, EI)
10. Liu S.-I. and C.-S. Hwang, 1997, Realization of current-mode filters using single FTFN, International Journal of Electronics, Vol. 82, pp. 499-502. (SCI, EI)

1. Chu T.-L., W.-Y. Chu, Y. Fujii and C.-S. Hwang*, 2015, All-digital deskew buffer using a hybrid control scheme, 2015 IEEE International SoC Conference, 2015/09/08-11, IEEE Circuits and Systems Society, Beijing, pp.30-34.
2. Hwang C.-S., T.-L. Chu and W.-C. Chen, 2014, A clock generator based on multiplying delay-locked loop, 2014 IEEE International SoC Conference, 2014/09/03-05, IEEE Circuits and Systems Society, Las Vegas.
3. Hwang, C.-S.*, T.-L. Chu and P.-H. Chen, 2013, DLL-based programmable clock multiplier using differential toggle-pulsed latch, 2013 IEEE International SoC Conference, 2013/09/04-06, IEEE Circuits and Systems Scociety, Erlangen, pp.239-243.
4. Chu T.-L., S.-H. Yu and C.-S. Hwang*, 2012, High-accuracy programmable timing generator with wide-range tuning capability, 2012 IEEE International Symposium on Intelligent Signal Processing and Communication Systems, 2012/11/04-07, Tamkang University, Taiwan, Taipei, Taiwan.
5. Chorng-Sii Hwang, Ting-Li Chu and Sin-Hong Yu, 2011, High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability, 2011 22nd VLSI/CAD Symposium, 2011/08/02-05, Taiwan Integrated Circuit Design Society, Yunlin County, pp.396-399.
6. Hwang, C.-S. and K.-H. Chen, 2009, Timing generator using dual delay-locked loop, 2009 IEEE Nuclear Science Symposium, 2009/10/25-31, IEEE Nuclear and Plasma Sciences Society, Orlando.
7. Hwang C.-S., C.-Y. Cho, C.-C. Chen, and H.-W. Tsao, 2009, Dual-band CDR using a half-rate linear phase detector, 2009 IEEE International SoC Conference, 2009/09/09-11, IEEE Circuits and Systems Society, Belfast.
8. Hwang C.-S., H.-C. Li and H.-W. Tsao, 2008, A spread spectrum clock generator using digital modulation scheme, 2008 IEEE International SoC Conference, 2008/09/17-20, Newport Beach, pp.337-340.
9. Hwang, C.-S., C.-W. Sung and H.-W. Tsao, 2007, Continuous time digitizer utilizing multiphase sampling technique, 2007 IEEE Nuclear Science Symposium, 2007/10/27-2007/11/03, IEEE Nuclear and Plasma Sciences Society, Honolulu, N15-55. (NSC 95-2221-E-224-103-)
10. Hwang, C.-S., C.-W. Sung and H.-W. Tsao, 2007, High-speed continuous time digitizer using a two-level multiphase sampling technique, 2007 International Conference on Communications, Circuits and Systems, 2007/07/11-13, Kokura, pp.1062-1066. (NSC 95-2221-E-224-103-)
11. Hwang C.-S., P. Chen, and H.-W. Tsao, 2004, A wide-range and fast-locking clock synthesizer IP based on delay-locked loop, 2004 IEEE International Symposium on Circuits and Systems, 2004/05/26-29, Vancouver, pp. 785-788.
12. Hwang C.-S., P. Chen, and H.-W. Tsao, 2003, A high-precision time-to-digital converter using a two-level conversion scheme, 2003 IEEE Nuclear Science Symposium, 2003/10/19-25, IEEE Nuclear and Plasma Sciences Society, Portland, pp. 174-176.
13. Hwang C.-S., P. Chen, and H.-W. Tsao, 2003, A high-resolution and fast-conversion time-to-digital converter, 2003 IEEE International Symposium on Circuits and Systems, 2003/05/25-28, Bangkok, pp. 25-28.
14. 張洧, 黃崇禧, 蔡志忠, 曹恆偉, 陳伯奇, 2002, 應用於可攜式雷射測距儀之低變異金氧半時間至數位轉換器, 2002臺灣光電科技研討會(論文集III), 2002/12/12-13, 臺北市, 台科大, pp. 133-135.
15. Hwang C.-S., W.-C. Chung, C.-Y. Wang, H.-W. Tsao and S.-I. Liu, 2000, A 2-V clock synchronizer using digital delay-locked loop, 2nd IEEE Asia Pacific Conference on ASIC, 2000/08/28-30, Cheju, pp. 91-94.
16. Hwang, C.-S., M.-H. Jiang, H.-W. Tsao and L.-C. Chen, 1999, A novel differential mode time-to-digital converter, 4th International Conference On Electronic Measurement and Instruments, 1999/08/18-21, Harbin, pp. 576-580.